What Is LID & PID?

What are LID and PID?

LID and PID are two distinct solar cell efficiency loss mechanisms that affect module output over time. Both are addressable through quality cell architecture and module construction, but both can degrade modules if mitigation is inadequate.

LID, Light-Induced Degradation, is a chemistry-driven efficiency reduction in silicon cells that occurs when sunlight first activates impurity-defect complexes inside the silicon. The effect is most pronounced in p-type silicon containing boron and oxygen impurities. LID manifests within the first hours to days of operation, then stabilises. Modern PERC cells limit LID to 1 to 2 percent of original efficiency; TOPCon and HJT (using n-type silicon) have even lower LID.

PID, Potential-Induced Degradation, is a separate longer-term degradation mechanism. It is caused by ion migration driven by the voltage potential between the cell circuit and the grounded module frame. PID can cause substantial output loss (up to 20+ percent in extreme cases) if modules are not PID-resistant by design. Quality Indian modules use PID-resistant cell architecture, encapsulant chemistry, and grounding schemes to prevent or minimise PID.

Why LID and PID matter

For module reliability, LID and PID are two of the cell-level effects that affect 25-year energy output. Mitigated PID is roughly invisible in lifetime kWh; unmitigated PID can destroy a project's economics.

For Indian field conditions, hot and humid climates accelerate PID. PID-resistant module design is especially important for Indian deployments. EPCs should confirm PID resistance specifications.

For warranty management, LID is typically included in first-year warranty caps (1 to 2 percent). PID failures trigger replacement warranty obligations.

For inverter selection, anti-PID features in inverters (positive or negative grounding) can mitigate PID. Some module-inverter pairings work better than others.

How LID and PID develop

1. Module installation. New modules with no operating history.
2. LID phase (first hours to days). Sunlight activates boron-oxygen defect complexes in p-type silicon. Small efficiency drop occurs and stabilises.
3. Stable operation. Module operates at stabilised efficiency.
4. PID risk emerges (weeks to years). Sustained high voltage difference between cell and frame drives ion migration through encapsulant.
5. PID symptoms. Output reduction visible as efficiency drop, sometimes asymmetric across the array.
6. Mitigation strategies. Anti-PID cell architecture, PID-resistant encapsulant, inverter grounding configuration.
7. Recovery (sometimes). Reverse-polarity treatment can recover some PID-induced loss.
8. Long-term operation. Properly mitigated modules show minimal LID/PID impact across 25 years.

Benefits of PID-resistant and low-LID modules

• Reliable long-term output. 25-year warranty trajectory protected.
• Lower first-year drop. Limit LID to 1 to 2 percent.
• Better Indian climate fit. PID resistance important in heat and humidity.
• Lender confidence. Standard module qualification covers LID/PID.
• Customer satisfaction. Field performance matches projections.

Limitations

Cannot fully eliminate LID. Even modern cells show some.

PID prevention depends on design. Skipping PID-resistant design risks degradation.

Recovery is partial. Reverse-polarity treatment helps but does not always restore full output.

Field detection delayed. PID symptoms can appear years after installation.

Inverter dependency. Grounding configuration affects PID susceptibility.

LID and PID in Indian modules

Aspect	Detail
LID in PERC modules	1 to 2 percent first-year drop typical
LID in TOPCon modules	Lower, typically 0.5 to 1 percent
LID in HJT modules	Very low
PID risk in hot/humid climates	Higher, mitigation important
PID-resistant design features	Anti-PID cells, EVA chemistry, grounding
Testing	IEC 62804 for PID
Warranty coverage	LID in first-year warranty; PID-related failures in product warranty

Quick facts

Term	LID & PID (Light-Induced Degradation & Potential-Induced Degradation)
LID timing	First hours to days after exposure
LID magnitude	0.5 to 2 percent of original output
PID timing	Weeks to years
PID magnitude (unmitigated)	Up to 20+ percent output loss
PID test standard	IEC 62804
Most affected cell	PERC with p-type silicon (more than TOPCon/HJT)
Mitigation	PID-resistant cell architecture + module design + inverter grounding

Common mistakes about LID and PID

1. Treating LID and PID as the same. Different mechanisms.
2. Ignoring PID in hot Indian climates. Major risk if unmitigated.
3. Skipping IEC 62804 verification. PID resistance should be confirmed.
4. Assuming all modules are PID-resistant. Quality varies.
5. Forgetting inverter grounding role. Affects PID susceptibility.
6. Quoting zero-LID projections. Modern modules have some, typically warranty-covered.
7. Treating PID recovery as guaranteed. Prevention is better than recovery.

Key takeaways

• LID is the small first-day output drop from chemistry in silicon cells (1 to 2 percent typical).
• PID is the longer-term output loss from voltage-induced ion migration (up to 20+ percent unmitigated).
• LID stabilises quickly; PID develops over weeks to years.
• TOPCon and HJT have lower LID than PERC; n-type silicon helps.
• Indian heat and humidity stress PID; mitigation is important.
• Quality module design includes PID-resistant cells, encapsulant, and grounding.
• IEC 62804 PID test verification matters for project lifetime reliability.

Frequently Asked Questions

Sources

• IEC 62804. PID test methodology.
• IEC 61215. Module qualification including LID stress.
• NREL. LID and PID research. nrel.gov
• Fraunhofer ISE. Cell-level degradation studies.
• Module manufacturer warranty documentation. LID coverage.
• Cell technology research publications. PERC, TOPCon, HJT LID comparisons.
• IS 14286. Indian module standard.